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CY22388/89/91
Factory Programmable Quad PLL Clock Generator with VCXO
Features
* Fully integrated phase-locked loops (PLLs) * QFN package: * 40% smaller than 20-pin TSSOP * 22% smaller than 16-pin TSSOP * Selectable Output Frequency * Programmable Output Frequencies * up t rq e c R n eo 5 1 6MH O tu Fe u n y a g f - 6 z * Input Frequency Range * rs l 0 3 MH C yt : - 0 z a1 * x ra R frn e 1 1 0MH E t n l eee c : - 0 e z * Analog VCXO * 16-/20-pin TSSOP and 32-pin QFN packages * 3.3V operation with 2.5V output buffer option
Benefits
* Meets most Digital Set Top Box, DVD Recorder, and DTV application requirements * Multiple high-performance PLLs allow synthesis of unrelated frequencies * Integration eliminates the need for external loop filter components * Meets critical timing requirements in complex system designs * Enables application compatibility * Complete VCXO solution with 120 ppm (typical pull range)
Block Diagram
C LK A
C LK B P LL1 C LK C X IN VC X O XOUT V IN P LL3 P LL2 D ivider & M ultiplexer C LK D
C LK E
C LK F P LL4 C LK G
C LK H FS 0/1/2 OE S elect Logic
Pin Configurations
16 -P in TS S O P X IN FS 0 FS 1 V IN VD D VSS C LK A C LK B 1 2 3 4 5 6 7 8 C Y 2 23 88 16 15 14 13 12 11 10 9 XOUT VDD FS2 VDD VSS C LK E C LK D C LK C
20-P in TSSO P
32 FS1 31 FS0
3 2 -P in Q F N
27 XOUT 26 VDD
X IN FS 0 FS 1 CLKH VDD VSS CLKD CLKB CLKA CLKC
1 2 3 4 5 C Y22389 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
XO UT VD D
V IN 1 2 3 4 5 6 7 8
25 VDD
NC 29
30 XIN
28
NC
24 23 22
O E /P D # FS2 VDD VDD VSS VSS C LK G C LK F
O E /P D FS2 VIN VD D VSS CLK G CLK F CLK E
VD D VD D VSS VSS VSS VSS C LKH
C Y22391
21 20 19 18 17
11
16
10 CLKB
12
13
14
15
CLKC
CLKD
CLKA
Cypress Semiconductor Corporation Document #: 38-07734 Rev. *B
* 198 Champion Court
* San Jose, CA 95134-1709 * 408-943-2600 Revised October 10, 2006
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CLKE
NC
NC
VDD
9
CY22388/89/91
Pin Description
Pin Name XIN XOUT CLKA CLKB CLKC CLKD CLKE CLKF CLKG CLKH FS0 FS1 FS2 OE/PD VIN VDD VSS NC Pin Number 16-Pin TSSOP 20-Pin TSSOP 1 16 7 8 9 10 11 n/a n/a n/a 2 3 14 n/a 4 5,13,15 6,12 n/a 1 20 9 8 10 7 11 12 13 4 2 3 17 18 16 5,15,19 6,14 n/a 32-Pin QFN 30 27 11 10 14 9 15 17 18 8 31 32 23 24 1 2,3,16,21,22,25,26 4,5,6,7,19,20 12,13,28,29 Pin Description Crystal Input or Reference Clock Input Crystal Output (No connect if external clock is used) Clock Output Clock Output Clock Output Clock Output Clock Output Clock Output Clock Output Clock Output Frequency Select 0 Frequency Select 1 Frequency Select 2 Output Enable Control/Power Down Analog Control Input for VCXO Voltage Supply Ground No Connect.
General Description
The CY22388 family of devices has an Analog VCXO (Voltage Controlled Crystal Oscillator), 4 PLLs, up to 8 clock outputs and frequency selection capabilities. The frequency selects do not modify any PLL frequency. Instead they allow the user to choose between up to 8 different output divider selections depending on the clock and package configuration. This is illustrated in the following Frequency Selection tables and Functional Block Diagram. There is one programmable OE/PDWN. The OE/PDWN pin can be programmed as either an output enable pin or a power-down pin. The OE function can be programmed to disable a selected set of outputs when low, leaving the remaining outputs running. Full-chip power down will disable all outputs as well as the PLLs and most of the active circuitry when low. Factory-Programmable CY22388/89/91 Factory programming is available for high- or low-volume manufacturing by Cypress. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number will be used for additional sample requests and production orders.
crystal. Generally a design may require up to four oscillators to accomplish what could be done with a single CY22388. Each PLL is independent and can be configured to generate a VCO (Voltage Controlled Oscillator) frequency between 62.5 MHz and 250 MHz. Each PLL can then in turn be divided down with post dividers to generate the clock output frequency o te u e' c o e T eo tu d i rao se c c c f h s r h i . h up t id lw a h l k s c ve l o output to be divided by 1,2,3,4,5,6,8,9,10,12,15. The PLL maximum is reduced to 166 MHz in divide by 1 mode due to output buffer limitations. Outputs that allow frequency switching perform the transition free of glitches. A glitch is defined as a high or low time shorter than half the smaller of the two periods being switched between. Extended low time (even many cycles in duration) is acceptable. Selected clock outputs are capable of being powered off a separate 2.5V supply. This will allow for driving lower voltage swing inputs. The CY22388/89/91 device still requires 3.3V to power the oscillator and all other internal PLL circuitry. For the 2.5V output option please refer to the CY22388 Application Note. Selected clocks and pinout diagrams will be explained in this application note. Clock D can obtain its output from either the reference source or PLL1/N1 with N1 being defined as the output divider for PLL1. Clock H is defined as a copy of clock D. Clock D is only available from PLL1/N1 on the 16-pin package. For CY22388, CLKB and CLKC have related frequencies. For CY22389 and CY22391, CLKD and CLKF have related frequencies, CLKA and CLKB have related frequencies, and Page 2 of 10
PLLs
The advantage of having four PLLs is that a single device can generate up to four independent frequencies from a single Document #: 38-07734 Rev. *B
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CY22388/89/91
CLKC and CLKE have related frequencies. Related frequencies come from the same PLL but can have different divider values. In order to minimize PPM (Parts Per Million) error on the clock outputs, a user should choose a crystal reference frequency that is a common multiple of the desired PLL frequencies. While this would be the ideal situation, this is not always the case and the PLLs have high-resolution counters internally to help minimize frequency deviation from the desired frequency. PLL VCO frequencies are generated by the following equation: FVCO = FREF * (P / Q) Where FREF is the reference input frequency, P is the PLL feedback divider and Q is the reference input divider. A PLL is a feedback system where the VCO frequency divided by P and reference frequency divided by Q are constantly being compared and the VCO frequency is adjusted to achieve a locked state. Figure 1 is a simplified drawing of a PLL. Figure 1.
F
Frequency Select Pin Operation
Table 1. CY22388 16-pin TSSOP Output Signal CLOCK A CLOCK B CLOCK C & CLOCK D CLOCK E Table 2. CY22389 20-pin TSSOP Output Signal CLOCK A CLOCK B & CLOCK C CLOCK G CLOCK H Frequency Selection Lines S2S1S0 S1S0 FIXED COPY OF CLOCK D Frequency Selection Lines S2S1S0 S1S0 S0 FIXED
CLOCK D, CLOCK E, & CLOCK F S0
REF
/Q
VCO
a nd
F
VCO
O th e r c o m p o n e n ts
Table 3. CY22391 32-pin QFN Output Signal Frequency Selection Lines S2S1S0 S1S0 FIXED COPY OF CLOCK D
/P
CLOCK A CLOCK B & CLOCK C CLOCK G CLOCK H
CLOCK D, CLOCK E, & CLOCK F S0
Document #: 38-07734 Rev. *B
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CY22388/89/91
Analog VCXO
There are three programmable reference operating modes for the CY22388/89/91 family of devices. The first mode utilizes an external pullable crystal and incorporates an internal Analog VCXO. The second mode configures the internal crystal oscillator to accept an external driven reference source from 1 to 100 MHz. The input capacitance on the XIN PIN when driven in this mode is 15 pF. The third mode disables the VCXO input control and sets the internal oscillator to a fixed frequency operation. The load capacitance seen by the external crystal when connected to PINS XIN and XOUT is equal to 12 pF. One of the key components to the CY22388/89/91 family of d v e i tea a gV X . h V X i u e t "u"h e i s s h n l C O T e C O s s d o p l te c o l reference crystal higher or lower in order to lock the system frequency to an external source. This is ideal for applications where the output frequency needs to track along with an external reference frequency that is constantly shifting. The VCXO is completely analog, so there is infinite resolution on the VCXO pull curve. The Analog to Digital Converter steps that are normally associated with a digital VCXO input is not present in this device. A special pullable crystal must be used to in order to have adequate VCXO pull range. Pullable Crystal specifications are included in this data sheet.
Please refer to the CY22388/89/91 Application Note for pullable crystal recommendations outside of the standard industry frequencies given in the Pullable Crystal Specifications.
VCXO Profile
Figure 2 shows an example of what a VCXO profile looks like. The analog voltage input is on the X-axis and the PPM range is on the Y-axis. An increase in the VCXO input voltage results in a corresponding increase in the output frequency. This has the effect of moving the PPM from a negative to positive offset. Figure 2. VCXO Profile .
200 150 100
Tuning [ppm]
50 0 -50 -100 -150 -200 VCXO input [V] 0 0.5 1 1.5 2 2.5 3 3.5
Document #: 38-07734 Rev. *B
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CY22388/89/91
Absolute Maximum Conditions
Parameter VIN TS ESDHBM UL-94 MSL Description Input Voltage Temperature, Storage ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Condition Relative to VSS Non-Functional MIL-STD-883, Method 3015 V-0 @1/8 in. QFN package 16- and 20-pin TSSOP Min. -. 05 -. 05 -5 6 2000 - 3 1 Max. 4.6 VDD + 0.5 +125 - 10 Unit V VDC C Volts ppm VDD/AVDD/VDDL Core Supply Voltage
Pullable Crystal Specifications[1, 3]
Parameter FNOM CLNOM R1 DL C0[2] C1[2] F3SEPHI
[3]
Description
Comments
Min.
Typ.
Max.
Unit
13.5-MHz and 27-MHz Crystal AT-Cut Parallel resonance, Fundamental mode Nominal Load Capacitance Equivalent Series Resistance (ESR) Crystal Drive Level Crystal Shunt Capacitance Crystal Motional Capacitance Third Overtone Separation from 3*FNOM Third Overtone Separation from 3*FNOM Mechanical Third (High side of 3*FNOM) Mechanical Third (Low side of 3*FNOM) Order crystal at one specific CLNOM 0 ppm Fundamental mode (CL = Series) Nominal VDD @ 25C over 120 PPM Pull Range 11.4 - - 1.5 12 240 -
See Note 3 12 - - 3 14 - - 12.6 40 300 4.0 16.8 - pF W pF fF ppm
F3SEPLO[3]
-2 1 0 ppm
Recommended Operating Conditions
Parameter VDD/AVDD/VDDL Operating Voltage TA CLOAD tPU Ambient Temperature Maximum Load Capacitance Power-up time for all VDDs reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.0 -0 1 - 0.05 Typ. 3.3 - - - Max. 3.6 70 15 500 Unit V C pF ms
Notes 1. Device operates to the following specs, which are guaranteed by design. 2. Increased tolerance available from pull range less than 120PPM. 3. Refer to CY22388 Application Note and online software for a list of Approved Crystal Specifications.
Document #: 38-07734 Rev. *B
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CY22388/89/91
DC Parameters[4]
Parameter IOH[5] IOL[5] IIH IIL VIH VIL VVCXO CIN IVDD CINXIN CINXTAL Description Output High Current Output Low Current Input High Current Input Low Current Input High Voltage Input Low Voltage VIN Input Range Input Capacitance Supply Current Input Capacitance at Crystal FS0/1/2 and OE Pins only VDD/AVDD/VDDL Current VCXO Disabled Fixed Freq. Oscillator Conditions VOH = VDD -05 V = 3.3V ., DD VOL = 0.5, VDD = 3.3V VIH = VDD, excluding Vin, Xin VIL = 0V, excluding Vin, Xin FS0/1/2 OE input CMOS levels FS0/1/2 OE input CMOS levels Min. 12 12 - - 0.7xAVDD - 0 - - - - Typ. - - 5 5 - - - - 60 15 12 Max. - - 10 10 - 0.3xAVDD AVDD 7 - - - Unit mA mA A A V V V pF mA pF pF
Input Capacitance at XIN VCXO Disabled External Reference
AC Parameters
Parameter[4] 1/t1 DC1 Description Output Frequency Output Duty Cycle (excluding REFOUT Output Duty Cycle Conditions PLL minmax/Dividermaximum Duty Cycle is defined in Figure 4; t2/t1, 50% of VDD Duty Cycle is defined in Figure 4; t2/t1, 50% of VDD Duty Cycle is defined in Figure 4; t2/t1, 50% of VDD (XIN Duty Cycle = 45/55%) Output Clock Edge Rate. Measured from 20% to 80% of VDD. CLOAD = 15 pF. See Figure 5. Output Clock Edge Rate. Measured from 80% to 20% of VDD. CLOAD = 15pF See Figure 5. Period Jitter
External reference duty cycle between 40% and 60% measured at VDD/2 (Clock output is 125 MHz)
Min. Typ. Max. Units 4.2 45 - 50 166 55 MHz %
DC2
40
50
60
%
External reference duty cycle between 40% and 60% measured at VDD/2 (Clock output is 125 MHz)
DCREFOUT ER EF T9 T10 f XO
Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time VCXO Crystal Pull Range
40 0.75 0.75 - -
50 1.2 1.2 250 1
60 - - - 5 - -
% V/ns V/ns ps ms ppm ppm
Using non- SMD-49 crystal specified in " Y 2 8 A pc t n 110 120 C 2 3 8 p lai io
N t, N 0 0 " oe A C 0 2 N t, N 0 0 " oe A C 0 2
Nominal Crystal Frequency Input assumed (0 ppm)@25C and 3.3V Using SMD-49 crystal specified in " Y 2 8 A pc t n C 2 3 8 p lai io Nominal Crystal Frequency Input assumed (0 ppm)@25C and 3.3V
105 120
Notes 4. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. 5. Custom Drive level and is available upon request
Document #: 38-07734 Rev. *B
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CY22388/89/91
Test and Measurement Set-up
Figure 3. Test and Measurement
V DDs DUT 0.1 F
O utputs C LO A D
GND
Voltage and Timing Definitions
Figure 4. Duty Cycle Definition t1 t2 V DD 50% of V DD Clock O utput 0V
Figure 5. ER = (0.6 VDD)/t3, EF = (0.6 DD)/t4 V t3 t4
V DD 80% of V DD
Clock O utput
20% of V DD 0V
Figure 6. FS Controlled Clock Output Finish Cycle Start at Full Cycle
FS TWAIT
Document #: 38-07734 Rev. *B
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CY22388/89/91
Ordering Information
Part Number[6] Lead-free CY22388ZXC-XXX CY22389ZXC-XXX CY22391LFXC-XXX 16-pin TSSOP 20-pin TSSOP 32-pin QFN Commercial, 0C to +70C Commercial, 0C to +70C Commercial, 0C to +70C Type Production Flow
Package Drawing and Dimensions
Figure 7. 16-lead TSSOP 4.40 mm Body Z16.173
51-85091-*A
Note 6. The CY22388ZXC-XXX, CY22389ZXC-xxx, and CY22391LFXC-xxx are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative.
Document #: 38-07734 Rev. *B
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CY22388/89/91
Figure 8. 20-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z20
51-85118-*A
Figure 9. 32-Lead QFN (5 x 5 mm) LF32A
51-85188-*A
All product and company names mentioned in this document are trademarks of their respective holder. Document #: 38-07734 Rev. *B Page 9 of 10
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY22388/89/91
Document History Page
Document Title: CY22388/89/91 Factory Programmable Quad PLL Clock Generator with VCXO Document Number: 38-07734 REV. ** *A ECN NO. 320458 389649 Issue Date See ECN See ECN Orig. of Change RGL RGL New data sheet Changed R1 value to max. 40 Changed DL comments and max. value to 300 W Changed f min. value to 110ppm and typ. value to 120ppm XO Specified a non-SMD-49 and SMD-49 crystal specs in the VCXO Pull Range Parameter Description of Change
*B
523597
See ECN
RGL
Document #: 38-07734 Rev. *B
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